Template:Streamline Pinout STM32F407

STM32 Alt	STM32	SL	Pin	Pin	SL	STM32	STM32 Alt
	GND		A1	B1		GND
	NRST		A2	B2		Boot0
	VBAT		A3	B3		VA
USART2_TX/TIM5_CH3 / TIM9_CH1 / TIM2_CH3 / ETH_MDIO / EVENTOUT / ADC123_IN2	PA2		A4	B4		PA3	USART2_RX/TIM5_CH4 / TIM9_CH2 / TIM2_CH4 / OTG_HS_ULPI_D0 / ETH_MII_COL / EVENTOUT / ADC123_IN3
USART2_RTS / UART4_RX / ETH_RMII_REF_CLK / ETH_MII_RX_CLK / TIM5_CH2 / TIM2_CH2/ EVENTOUT / ADC123_IN1	PA1		A5	B5	SPI1	PA4	SPI1_NSS / SPI3_NSS / USART2_CK / DCMI_HSYNC / OTG_HS_SOF/ I2S3_WS / EVENTOUT / ADC12_IN4 / DAC_OUT1
USART2_CTS / UART4_TX / ETH_MII_CRS / TIM2_CH1_ETR / TIM5_CH1 / TIM8_ETR / EVENTOUT / ADC123_IN0 / WKUP	PA0		A6	B6	SPI1	PA5	SPI1_SCK / OTG_HS_ULPI_CK / TIM2_CH1_ETR / TIM8_CH1N / EVENTOUT / ADC12_IN5 / DAC_OUT2
SPI2_MOSI / I2S2_SD / OTG_HS_ULPI_NXT / ETH_MII_TX_CLK/ EVENTOUT / ADC123_IN13	PC3		A7	B7	SPI1	PA6	SPI1_MISO / TIM8_BKIN/TIM13_CH1 / DCMI_PIXCLK / TIM3_CH1 / TIM1_BKIN / EVENTOUT / ADC12_IN6
SPI2_MISO / OTG_HS_ULPI_DIR / ETH_MII_TXD2 / I2S2ext_SD/ EVENTOUT / ADC123_IN12	PC2		A8	B8	SPI1	PA7	SPI1_MOSI / TIM8_CH1N / TIM14_CH1/TIM3_CH2 / ETH_MII_RX_DV / TIM1_CH1N / ETH_RMII_CRS_DV / EVENTOUT / ADC12_IN7
ETH_MDC/ EVENTOUT / ADC123_IN11	PC1		A9	B9		PC4	ETH_RMII_RX_D0 / ETH_MII_RX_D0 / EVENTOUT / ADC12_IN14
OTG_HS_ULPI_STP / EVENTOUT / ADC123_IN10	PC0		A10	B10		PC5	ETH_RMII_RX_D1 / ETH_MII_RX_D1 / EVENTOUT / ADC12_IN15
OSC32_OUT	PC15		A11	B11		PB0	TIM3_CH3 / TIM8_CH2N / OTG_HS_ULPI_D1 / ETH_MII_RXD2 / TIM1_CH2N / EVENTOUT / ADC12_IN8
OSC32_IN	PC14		A12	B12		PB1	TIM3_CH4 / TIM8_CH3N / OTG_HS_ULPI_D2 / ETH_MII_RXD3 / TIM1_CH3N / EVENTOUT / ADC12_IN9
RTC_OUT / RTC_TAMP1 / RTC_TS	PC13		A13	B13		PB2	EVENTOUT / BOOT1
TRACED3 / FSMC_A22 / TIM9_CH2 / DCMI_D7 / EVENTOUT	PE6		A14	B14		PE7	FSMC_D4 / TIM1_ETR / EVENTOUT
TRACED2 / FSMC_A21 / TIM9_CH1 / DCMI_D6 / EVENTOUT	PE5		A15	B15		PE8	FSMC_D5 / TIM1_CH1N / EVENTOUT
TRACED1/FSMC_A20 / DCMI_D4/ EVENTOUT	PE4		A16	B16		PE9	FSMC_D6 / TIM1_CH1 / EVENTOUT
TRACED0 / FSMC_A19 / EVENTOUT	PE3		A17	B17		PE10	FSMC_D7 / TIM1_CH2N / EVENTOUT
TRACECLK/ FSMC_A23 / ETH_MII_TXD3 / EVENTOUT	PE2		A18	B18		PE11	FSMC_D8 / TIM1_CH2 / EVENTOUT
	U1		A19	B19		U2
TIM4_ETR / FSMC_NBL0 / DCMI_D2/ EVENTOUT	PE0		A20	B20		PE12	FSMC_D9 / TIM1_CH3N / EVENTOUT
FSMC_NBL1 / DCMI_D3 / EVENTOUT	PE1		A21	B21		PE13	FSMC_D10 / TIM1_CH3 / EVENTOUT
SPI2_NSS / I2S2_WS / TIM4_CH4 / TIM11_CH1 / SDIO_D5 / DCMI_D7 / I2C1_SDA / CAN1_TX / EVENTOUT	PB9		A22	B22		PE14	FSMC_D11 / TIM1_CH4 / EVENTOUT
TIM4_CH3 / SDIO_D4 / TIM10_CH1 / DCMI_D6 / ETH_MII_TXD3 / I2C1_SCL / CAN1_RX / EVENTOUT	PB8		A23	B23		PE15	FSMC_D12 / TIM1_BKIN / EVENTOUT
I2C1_SDA / FSMC_NL / DCMI_VSYNC / USART1_RX / TIM4_CH2 / EVENTOUT	PB7		A24	B24		PB10	SPI2_SCK / I2S2_CK / I2C2_SCL / USART3_TX / OTG_HS_ULPI_D3 / ETH_MII_RX_ER / TIM2_CH3 / EVENTOUT
I2C1_SCL / TIM4_CH1 / CAN2_TX / DCMI_D5 / USART1_TX / EVENTOUT	PB6		A25	B25		PB11	I2C2_SDA / USART3_RX / OTG_HS_ULPI_D4 / ETH_RMII_TX_EN / ETH_MII_TX_EN / TIM2_CH4 / EVENTOUT
I2C1_SMBA/ CAN2_RX / OTG_HS_ULPI_D7 / ETH_PPS_OUT / TIM3_CH2 / SPI1_MOSI / SPI3_MOSI / DCMI_D10 / I2S3_SD / EVENTOUT	PB5		A26	B26	SPI2	PB12	SPI2_NSS / I2S2_WS / I2C2_SMBA / USART3_CK / TIM1_BKIN / CAN2_RX / OTG_HS_ULPI_D5 / ETH_RMII_TXD0 / ETH_MII_TXD0 / OTG_HS_ID / EVENTOUT
	U3		A27	B27		U4
NJTRST / SPI3_MISO / TIM3_CH1 / SPI1_MISO / I2S3ext_SD / EVENTOUT	PB4		A28	B28	SPI2	PB13	SPI2_SCK / I2S2_CK / USART3_CTS / TIM1_CH1N / CAN2_TX / OTG_HS_ULPI_D6 / ETH_RMII_TXD1 / ETH_MII_TXD1 / EVENTOUT / OTG_HS_VBUS
JTDO / TRACESWO / SPI3_SCK / I2S3_CK / TIM2_CH2 / SPI1_SCK / EVENTOUT	PB3	SWO	A29	B29	SPI2	PB14	SPI2_MISO / TIM1_CH2N / TIM12_CH1 / OTG_HS_DM / USART3_RTS / TIM8_CH2N / I2S2ext_SD / EVENTOUT
USART2_CK / FSMC_NE1 / FSMC_NCE2 / EVENTOUT	PD7		A30	B30	SPI2	PB15	SPI2_MOSI / I2S2_SD / TIM1_CH3N / TIM8_CH3N / TIM12_CH2 / OTG_HS_DP/ EVENTOUT / RTC_REFIN
FSMC_NWAIT / USART2_RX / EVENTOUT	PD6		A31	B31		PD8	FSMC_D13 / USART3_TX / EVENTOUT
FSMC_NWE / USART2_TX / EVENTOUT	PD5		A32	B32		PD9	FSMC_D14 / USART3_RX / EVENTOUT
FSMC_NOE / USART2_RTS / EVENTOUT	PD4		A33	B33		PD10	FSMC_D15 / USART3_CK / EVENTOUT
FSMC_CLK / USART2_CTS / EVENTOUT	PD3		A34	B34		PD11	FSMC_CLE / FSMC_A16 / USART3_CTS / EVENTOUT
TIM3_ETR / UART5_RX / SDIO_CMD / DCMI_D11 / EVENTOUT	PD2		A35	B35		PD12	FSMC_ALE / FSMC_A17 / TIM4_CH1 / USART3_RTS / EVENTOUT
FSMC_D3 / CAN1_TX / EVENTOUT	PD1	CAN1	A36	B36		PD13	FSMC_A18 / TIM4_CH2 / EVENTOUT
FSMC_D2 / CAN1_RX / EVENTOUT	PD0	CAN1	A37	B37		PD14	FSMC_D0 / TIM4_CH3 / EVENTOUT
	U5		A38	B38		U6
UART5_TX / SDIO_CK / DCMI_D9 / SPI3_MOSI / I2S3_SD / USART3_CK / EVENTOUT	PC12		A39	B39		PD15	FSMC_D1 / TIM4_CH4 / EVENTOUT
UART4_RX / SPI3_MISO / SDIO_D3 / DCMI_D4/USART3_RX / I2S3ext_SD / EVENTOUT	PC11		A40	B40		PC6	I2S2_MCK / TIM8_CH1/SDIO_D6 / USART6_TX / DCMI_D0/TIM3_CH1 / EVENTOUT
SPI3_SCK / I2S3_CK / UART4_TX / SDIO_D2 / DCMI_D8 / USART3_TX / EVENTOUT	PC10		A41	B41		PC7	I2S3_MCK / TIM8_CH2/SDIO_D7 / USART6_RX / DCMI_D1/TIM3_CH2 / EVENTOUT
JTDI / SPI3_NSS / I2S3_WS / TIM2_CH1_ETR / SPI1_NSS / EVENTOUT	PA15		A42	B42		PC8	TIM8_CH3 / SDIO_D0 / TIM3_CH3 / USART6_CK / DCMI_D2 / EVENTOUT
JTCK-SWCLK / EVENTOUT	PA14	SWD	A43	B43		PC9	I2S_CKIN / MCO2 / TIM8_CH4/SDIO_D1 / I2C3_SDA / DCMI_D3 / TIM3_CH4 / EVENTOUT
USART1_CTS / CAN1_RX / TIM1_CH4 / OTG_FS_DM / EVENTOUT	PA11	USB	A44	B44		PA8	MCO1 / USART1_CK / TIM1_CH1 / I2C3_SCL / OTG_FS_SOF / EVENTOUT
USART1_RTS / CAN1_TX / TIM1_ETR / OTG_FS_DP / EVENTOUT	PA12	USB	A45	B45		PA9	USART1_TX / TIM1_CH2 / I2C3_SMBA / DCMI_D0 / EVENTOUT / OTG_FS_VBUS
JTMS-SWDIO / EVENTOUT	PA13	SWD	A46	B46		PA10	USART1_RX/ TIM1_CH3 / OTG_FS_ID / DCMI_D1 / EVENTOUT
	3V3		A47	B47		3V3
	5V		A48	B48		5V
	GND		A49	B49		GND