Streamline Peripheral Pin Mapping

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General notes

field means that all MCUs can be mapped identically.

field means it is missing the peripheral.

field means that pins are not same across all MCUs.

field is I2Sx_MCK only exist on one pin.

RP2350

Trying to avoid 12 - 19 as these can be used for HSTX but they should be wired to backplane.

SWD

Variant PIN STM32F407 STM32L475 STM32H562 STM32C071 STM32C551 STM32H723 RP2354 Remarks
All SWDIO PA13 PA13 PA13 PA13 PA13 PA13 SWDIO RP Pico Dedicated pin
SWCLK PA14 PA14 PA14 PA14 PA14 PA14 SWCLK
SWO PB3 PB3 PB3 N/A PB3 PB3 TBD N/A

UARTs

  • RP2350 UART0 TX: 0 / 12 / 16 / 28 / 32 / 44
  • RP2350 UART0 RX: 1 / 13 / 17 / 29 / 33 / 45
  • RP2350 UART1 TX: 4 / 8 / 20 / 24 / 36 / 40
  • RP2350 UART1 RX: 5 / 9 / 21 / 25 / 37 / 41
Variant PIN STM32F407 STM32L475 STM32H562 STM32C071 STM32C551 STM32H723 RP2354 Remarks
USART1 TX PA9 PA9 PA9 PA9 PA9 PA9 0 Connect default
RP2350 UART0
RX PA10 PA10 PA10 PA10 PA10 PA10 1
USART1A TX PB6 PB6 PB6 PB6 PB6 PB6
RX PB7 PB7 PB7 PB7 PB7 PB7
USART2 TX PA2 PA2 PA2 PA2 PA2 PA2 4 RP2350 UART1
RX PA3 PA3 PA3 PA3 PA3 PA3 5
USART2A TX PD5 PD5 PD5 PD5 PD5 PD5
RX PD6 PD6 PD6 PD6 PD6 PD6
USART3 TX PB10 PB10 PB10 N/A PB10 PB10
RX PB11 PB11 PB11 N/A PB11 PB11
USART3A1 TX PD8 PD8 PD8 N/A PD8 PD8
RX PD9 PD9 PD9 N/A PD9 PD9
USART3A2 TX PC10 PC10 PC10 N/A PC10 PC10 N/A
RX PC11 PC11 PC11 N/A PC11 PC11 N/A
UART4 TX PA0 PA0 PA0 N/A PA0 PA0
RX PA1 PA1 PA1 N/A PA1 PA1
UART4A TX PC10 PC10 PC10 N/A PC10 PC10
RX PC11 PC11 PC11 N/A PC11 PC11
UART5 TX PC12 PC12 PC12 N/A PC12 PC12 TBD
RX PD2 PD2 PD2 N/A PD2 PD2 TBD
USART6 TX PC6 N/A PC6 N/A N/A PC6 TBD
RX PC7 N/A PC7 N/A N/A PC7 TBD

CAN

Variant PIN STM32F407 STM32L475 STM32H562 STM32C071 STM32C551 STM32H723 RP2354
CAN1 TX PA12 PA12 PA12 N/A PA12 PA12 TBD
RX PA11 PA11 PA11 N/A PA11 PA11 TBD
CAN1A TX PD1 PD1 PD1 N/A PD1 PD1 TBD
RX PD0 PD0 PD0 N/A PD0 PD0 TBD
CAN2 TX PB13 N/A PB13 N/A N/A PB13 TBD
RX PB12 N/A PB13 N/A N/A PB13 TBD
CAN2A TX PB6 N/A PB6 N/A N/A PB6 TBD
RX PB5 N/A PB6 N/A N/A PB6 TBD

USB

STM32F407=HS/FS host/device/otg

STM32L475=FS host/device/otg no crystal

STM32H562=FS PD

STM32C071=FS no crystal

STM32C551=FS host/device

STM32H723=HS/FS host/device/otg

RP2354=FS host/device

Variant PIN STM32F407 STM32L475 STM32H562 STM32C071 STM32C551 STM32H723 RP2354 Remarks
All DM PA11 PA11 PA11 PA11 PA11 PA11 DM RP2350 dedicated pins
DP PA12 PA12 PA12 PA12 PA12 PA12 DP

I2C

  • RP2350 I2C0 SCL: 1 / 5 / 9 / 13 / 17 / 21 / 25 / 29 / 33 / 37 / 41 / 45
  • RP2350 I2C0 SDA: 0 / 4 / 8 / 12 / 16 / 20 / 24 / 28 / 32 / 36 / 40 / 44
  • RP2350 I2C1 SCL: 3 / 7 / 11 / 15 / 19 / 23 / 27 / 31 / 35 / 39 / 43 / 47
  • RP2350 I2C1 SDA: 2 / 6 / 10 / 14 / 18 / 22 / 26 / 30 / 34 / 38 / 42 / 46
Variant PIN STM32F407 STM32L475 STM32H562 STM32C071 STM32C551 STM32H723 RP2354 Remarks
I2C1 SCL PB6 PB6 PB6 PB6 PB6 PB6 9 RP2350 ICL0
SDA PB7 PB7 PB7 PB7 PB7 PB7 8
I2C1A SCL PB8 PB8 PB8 PB8 PB8 PB8 TBD
SDA PB9 PB9 PB9 PB9 PB9 PB9 TBD
I2C2 SCL PB10 PB10 PB10 PB10 PB10 PB10 3 RP2350 I2C1
SDA PB11 PB11 PB11 PB11 PB11 PB11 2
I2C3 SCL PA8 PC0 PA8 N/A N/A PA8 TBD
SDA PC9 PC1 PC9 N/A N/A PC9 TBD

SPI

  • RP2350 SPI0 SCK: 2 / 6 / 18 / 22 / 34 / 38
  • RP2350 SPI0 MISO: 0 / 4 / 16 / 20 / 32 / 36
  • RP2350 SPI0 MOSI: 3 / 7 / 19 / 23 / 35 / 39
  • RP2350 SPI1 SCK: 10 / 14 / 26 / 30 / 42 / 46
  • RP2350 SPI1 MISO: 8 / 12 / 24 / 28 / 40 / 44
  • RP2350 SPI1 MOSI: 11 / 15 / 27 / 31 / 43 / 47
Variant PIN STM32F407 STM32L475 STM32H562 STM32C071 STM32C551 STM32H723 RP2354 Remarks
SPI1 SCK PA5 PA5 PA5 PA5 PA5 PA5 22 RP2350 SPI0
MISO PA6 PA6 PA6 PA6 PA6 PA6 20
MOSI PA7 PA7 PA7 PA7 PA7 PA7 23
SPI1A SCK PB3 PB3 PB3 PB3 PB3 PB3 TBD Conflicts with SWO
MISO PB4 PB4 PB4 PB4 PB4 PB4 TBD
MOSI PB5 PB5 PB5 PB5 PB5 PB5 TBD
SPI2 SCK PB10 PB10 PB10 PB10 PB10 PB10 10 RP2350 SPI1
MISO PC2 PC2 PC2 PC2 PC2 PC2 8
MOSI PC3 PC3 PC3 PC3 PC3 PC3 11
SPI2A SCK PB13 PB13 PB13 PB13 PB13 PB13 TBD
MISO PB14 PB14 PB14 PB14 PB14 PB14 TBD
MOSI PB15 PB15 PB15 PB15 PB15 PB15 TBD
SPI3 SCK PC10 PC10 PC10 N/A PC10 PC10 TBD
MISO PC11 PC11 PC11 N/A PC11 PC11 TBD
MOSI PC12 PC12 PC12 N/A PC12 PC12 TBD
SPI3A SCK PB3 PB3 PB3 N/A PB3 PB3 TBD Conflicts with SWO
MISO PB4 PB4 PB4 N/A PB4 PB4 TBD
MOSI PB5 PB5 PB5 N/A PB5 PB5 TBD

SDIO

STM32F407: SDIO

STM32L475: SDMMC

STM32H562: SDMMC

STM32C071: N/A

STM32C551: N/A

STM32H723: SDMMC

Variant PIN STM32F407 STM32L475 STM32H562 STM32C071 STM32C551 STM32H723 RP2354
Only CMD PD2 PD2 PD2 N/A N/A PD2 TBD
CK PC12 PC12 PC12 N/A N/A PC12 TBD
D0 PC8 PC8 PC8 N/A N/A PC8 TBD
D1 PC9 PC9 PC9 N/A N/A PC9 TBD
D2 PC10 PC10 PC10 N/A N/A PC10 TBD
D3 PC11 PC11 PC11 N/A N/A PC11 TBD

ULPI

STM32F407: ULPI

STM32L475: N/A

STM32H562: N/A

STM32C071: N/A

STM32C551: N/A

STM32H723: ULPI

Variant PIN STM32F407 STM32L475 STM32H562 STM32C071 STM32C551 STM32H723 RP2354
Only STP PC0 N/A N/A N/A N/A PC0 N/A
DIR PC2 N/A N/A N/A N/A PC2 N/A
NXT PC3 N/A N/A N/A N/A PC3 N/A
CK PA5 N/A N/A N/A N/A PA5 N/A
D0 PA3 N/A N/A N/A N/A PA3 N/A
D1 PB0 N/A N/A N/A N/A PB0 N/A
D2 PB1 N/A N/A N/A N/A PB1 N/A
D3 PB10 N/A N/A N/A N/A PB10 N/A
D4 PB11 N/A N/A N/A N/A PB11 N/A
D5 PB12 N/A N/A N/A N/A PB12 N/A
D6 PB13 N/A N/A N/A N/A PB13 N/A
D7 PB5 N/A N/A N/A N/A PB5 N/A

I2S

STM32F407: I2S2, I2S3

STM32L475: SAI1, SAI2 (serial audio interface)

STM32H562: I2S1, I2S2, I2S3

STM32C071: I2S1 (half duplex only)

STM32C551: I2S1, I2S2, I2S3

STM32H723: I2S1, I2S2, I2S3

Variant PIN STM32F407 STM32L475 STM32H562 STM32C071 STM32C551 STM32H723 RP2354
I2S1 MCK N/A PB8 PC4 PA6, PA11, PD5, PB4, PB6 PC4 PC4 TBD
SDI N/A PB5 PA6 PA2,PA7,PA12,PB5,PD6,PB6†† PA6 PA6 TBD
SDO N/A PC3 PA7 PA7 PA7 PA7 TBD
CK N/A PB10 PA5 PA5 PA5 PA5 TBD
WS N/A PB9 PA4 PA1,PA5,PD8,PB3,PB6 PA4 PA4 TBD
I2S2 MCK PC6 PB14 PC6 N/A PC6 PC6 TBD
SDI PC2 PC12 PC2 N/A PC2 PC2 TBD
SDO PC3 PD11 PC3 N/A PC3 PC3 TBD
CK PB10 PD10 PB10 N/A PB10 PB10 TBD
WS PB12 PB12 PB12 N/A PB12 PB12 TBD
I2S2a MCK N/A PD9 N/A N/A N/A N/A TBD
SDI PB14 N/A PB14 N/A PB14 PB14 TBD
SDO PB15 PB15 PB15 N/A PB15 PB15 TBD
CK PB13 PB13 PB13 N/A PB13 PB13 TBD
WS PB9 PB9 PB9 N/A PB9 PB9 TBD
I2S3 MCK PC7 N/A PC7 N/A PC7 PC7 TBD
SDI PC11 N/A PC11 N/A PC11 PC11 TBD
SDO PC12 N/A PC12 N/A PC12 PC12 TBD
CK PC10 N/A PC10 N/A PC10 PC10 TBD
WS PA4 N/A PA4 N/A PA4 PA4 TBD
I2S3a MCK N/A N/A N/A N/A N/A N/A TBD
SDI PB4 N/A PB4 N/A PB4 PB4 TBD
SDO PB5 N/A PB5 N/A PB5 PB5 TBD
CK PB3 N/A PB3 N/A PB3 PB3 TBD
WS PA15 N/A PA15 N/A PA15,PB8,PE4 ††† PA15 TBD

Notes;

†† The STM32C071 has only one half-duplex I2S, and the _SD pin can either be in INPUT or OUTPUT mode. Many pins, how do we map?

††† I2S3_WS is ONLY mapped on PA15 (used for SWDIO), except on STM32C551 which ALSO has it on PB8.

DACs

Variant PIN STM32F407 STM32L475 STM32H562 STM32C071 STM32C551 STM32H723 RP2354
DAC1 OUT1 PA4 PA4 PA4 N/A PA4 PA4 N/A
OUT2 PA5 PA5 PA5 N/A N/A PA5 N/A

ADCs

ADCs are so numerous that comparative tables are difficult to establish.

STM32F407; 12 channels common for ADC1, ADC2 and ADC3. 4 channels for ADC1 and ADC2

STM32F407; 4 channels common for ADC1, ADC2 and ADC3. 12 channels for ADC1 and ADC2

STM32H562; All 16 channels common for ADC1 and ADC2, can also be configured as 8 differential pair inputs.

STM32C071; Only ADC1, 19 external channels.

STM32C551; 7 channels common for ADC1 and ADC2.

STM32H723; ADC1 and ADC2 are 16 bits, ADC3 is 12 bits. All 3 can also be configured as 8 differential pair inputs.

RP2354; One ADC, 12 bits, 0.5 Msps

Variant PIN STM32F407 STM32L475 STM32H562 STM32C071 STM32C551 STM32H723 RP2354
ADC1 Pins PA0-PA7,PC0-PC5,PB0-PB1 PA0-PA7,PC0-PC5,PB0-PB1 PA0-PA7,PC0-PC5,PB0-PB1 PA0-PA8,PA13-PA14,PC0-PC5,PB0-PB2,PB10-PB12 PA0-PA7,PC0-PC3 PA0-PA7,PC0-PC2,PC4-PC5,PB0-PB1 GPIO40-GPIO47
Channels 16 16 16 19 12 15 8
Msps 2.4 5 5 2.5 2.25 3.6 0.5
ADC2 Pins PA0-PA7,PC0-PC5,PB0-PB1 PA0-PA7,PC0-PC5,PB0-PB1 PA0-PA7,PC0-PC5,PB0-PB1 N/A PA0-PA3,PC1-PC5,PB0-PB2 PA2-PA7,PC0-PC2,PC4-PC5,PB0-PB1 N/A
Channels 16 16 16 N/A 12 13 N/A
Msps 2.4 5 5 N/A 2.25 3.6 N/A
ADC3 Pins PA0-PA7,PC0-PC3 PC0-PC3 N/A N/A N/A PC0-PC3 N/A
Channels 6 4 N/A N/A N/A 4 (12 bits) N/A
Msps 2.4 5 N/A N/A N/A 5 N/A
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