Difference between revisions of "Almost as Simple as Possible (8-bit CPU)"

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== Miscellaneous Links ==  
 
== Miscellaneous Links ==  

Revision as of 10:15, 22 November 2022

About 6 years ago (at the time of writing), Ben Eater started a series of Youtube videos (see here, where he is building a very simple (but complete) 8 bit computer on a breadboard using almost exclusively discrete logic chips. Since then, this simple design has attracted a huge following and a lot of people have developed something similar. It has even gotten to a point where the original design has gotten itself a name - most people call it SAP-1 (Simple as Possible) although I don't think Ben Eater ever used that name himself.

I can not stress enough how big an inspiration those videos has been to me (and if you have not watched them, quit reading this page and go watch them now) and ever since watching them I have wanted to build one myself. However, I absolutely hate breadboards with a vengeance, so building SAP-1 on a breadboard was for me never a real option.

I was toying around with the idea of starting a series of PCB's putting the different modules together. This idea was/is attractive to me but the problem is that the old TTL/CMOS logic chips are getting quite expensive and some are hard to get.

Fortunately, a third option presented itself, when I got my hands on a ColorLight I5 module with accompanying extension board. With 25000 logic units, this FPGA is plenty big enough to implement something like this, and doing it in a FPGA will keep my desk way less messy than doing it on a breadboard.

Compared with Ben Eater's design, I made a few tentative decisions:

  • All logic "active high"
Ben Eater's design uses standard logic chips and these often use active low for signals like chip select and output enable. On a FPGA there's absolutely no reason to do this.
  • 256 byte memory
The original design had a shared program/memory space of 16 byte. This was done for a number of reasons.

Clock

The ColorLight I5 has got a 25 MHz crystal oscillator.

Freq Divider
0.1 Hz 125,000,000
1 Hz 12,500,000
1 kHz 12,500
1 MHz 12 (ish)

I/O Button and LED Board

Monitoring all busses

Gallery

Miscellaneous Links