Difference between revisions of "FPGA"
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[[#Synthesis|Synthesis]] refers to the process of translating [[Verilog]] source. | [[#Synthesis|Synthesis]] refers to the process of translating [[Verilog]] source. | ||
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| + | ==== Yosys ==== | ||
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| + | * [https://github.com/YosysHQ/yosys Yosys Github Repository] | ||
