Difference between revisions of "Stm32Dev - rev. b (GD32F405 variant)"
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+ | |||
+ | == Timer Interrupt == | ||
+ | |||
+ | Simple test if the timers - including timer interrupt - is running as expected. | ||
+ | |||
+ | Configured TIM4 as follows: | ||
+ | |||
+ | [[File:GD405 timer 4.png|400px]] | ||
+ | |||
+ | Created a simple call back: | ||
+ | |||
+ | <pre> | ||
+ | /* USER CODE BEGIN 0 */ | ||
+ | // Override the weak call back function | ||
+ | void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { | ||
+ | if (htim->Instance == TIM4) { | ||
+ | HAL_GPIO_TogglePin(CLK_GPIO_Port, CLK_Pin); | ||
+ | } | ||
+ | } | ||
+ | /* USER CODE END 0 */ | ||
+ | </pre> | ||
+ | |||
+ | The APB1 timer clock is 84 MHz, so in theory this should result in a 5 KHz clock on the CLK pin. | ||
+ | |||
+ | [[File:Timer on scope.jpg|600px]] | ||
+ | |||
+ | Which is spot on. |
Revision as of 04:22, 12 May 2021
To further test compatibility between stm32 and gd32 processors, I ordered a batch of Stm32Dev boards with the STM32F405RGT6 MCU replaced with a GD32F405RGT6.
To be absolutely certain that the boards were identical, the same gerbers were used, with only the bom modified (even down to the spelling mistake on the silk screen).
The point of this is to investigate if the GD32F4xx is drop in compatible with the STM32F4xx.
Flashing
To do a command line flash, I usually use the st-flash command.
DFU
It is a little unclear if DFU is supported.
There is no mention of DFU in any of the manuals, but in the datasheet the following is stated:
However, in the user manual it says:
The device refuse to show up as a DFU device, so I'll assume DFU is not supported.
Physical Device
Timer Interrupt
Simple test if the timers - including timer interrupt - is running as expected.
Configured TIM4 as follows:
Created a simple call back:
/* USER CODE BEGIN 0 */ // Override the weak call back function void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { if (htim->Instance == TIM4) { HAL_GPIO_TogglePin(CLK_GPIO_Port, CLK_Pin); } } /* USER CODE END 0 */
The APB1 timer clock is 84 MHz, so in theory this should result in a 5 KHz clock on the CLK pin.
Which is spot on.