Verilog

At the moment I just use this page to jot down unstructured bits and pieces. Notice, I am an absolute beginner and inexperienced with Verilog, so do not interpret anything on this page as gospel.

Assign vs. Always

Basically assign statements are used to connect different devices via nets. Always blocks are used to express behavior of those devices.

In general the 'assign' statements are used to assign values to nets. always blocks deal with assigning values to registers.

Miscellaneous Links

• FPGA designs with Verilog