Difference between revisions of "Verilog"
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[[Category:FPGA]][[Category:Work in progress]] | [[Category:FPGA]][[Category:Work in progress]] | ||
At the moment I just use this page to jot down unstructured bits and pieces. Notice, I am an absolute beginner and inexperienced with [[Verilog]], so do not interpret anything on this page as gospel. | At the moment I just use this page to jot down unstructured bits and pieces. Notice, I am an absolute beginner and inexperienced with [[Verilog]], so do not interpret anything on this page as gospel. | ||
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| + | == Wires vs. Registers == | ||
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| + | Wires need to be driven. They can be driven from a continuous assignment or from a register. | ||
== Assign vs. Always == | == Assign vs. Always == | ||
Latest revision as of 09:13, 9 July 2023
At the moment I just use this page to jot down unstructured bits and pieces. Notice, I am an absolute beginner and inexperienced with Verilog, so do not interpret anything on this page as gospel.
Wires vs. Registers
Wires need to be driven. They can be driven from a continuous assignment or from a register.
Assign vs. Always
Basically assign statements are used to connect different devices via nets. Always blocks are used to express behavior of those devices.
In general the 'assign' statements are used to assign values to nets. always blocks deal with assigning values to registers.