Difference between revisions of "Verilog"
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| − | [[Category:FPGA]] | + | [[Category:FPGA]][[Category:Work in progress]] |
| + | At the moment I just use this page to jot down unstructured bits and pieces: | ||
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| + | == Assign vs. Always == | ||
| + | |||
| + | Basically assign statements are used to connect different devices via nets. Always blocks are used to express behavior of those devices. | ||
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| + | In general the 'assign' statements are used to assign values to nets. always blocks deal with assigning values to registers. | ||
== Miscellaneous Links == | == Miscellaneous Links == | ||
* [https://verilogguide.readthedocs.io/en/latest/ FPGA designs with Verilog] | * [https://verilogguide.readthedocs.io/en/latest/ FPGA designs with Verilog] | ||
Revision as of 10:38, 2 January 2023
At the moment I just use this page to jot down unstructured bits and pieces:
Assign vs. Always
Basically assign statements are used to connect different devices via nets. Always blocks are used to express behavior of those devices.
In general the 'assign' statements are used to assign values to nets. always blocks deal with assigning values to registers.